1984/01/01 by Saumitra Mehrotra, Tsung-Ching Wu, Te-Long Chiu +1 · 1 citation
Engineering · #Semiconductor materials and devices #Advancements in Semiconductor Devices and Circuit Design #Analog and Mixed-Signal Circuit Design
paper · doi:10.1109/isscc.1984.1156662
openalex publication_date 1984/01/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/29
A 5V-only 64Kb EEROM using a 1.5μm N-well CMOS on epi technology, and featuring a 85μm2two-transistor cell and 33100 mil2die area, will be reported. Address edge detection circuit techniques have resulted in a 100ns typical access time at 50mW active power dissipation.