2017/09/01 by Jin Hee Kim, Brett Grady, Ruolong Lian +2 · 1 voice
Computer Science · Engineering · Mathematics · #Advanced Memory and Neural Computing #Advanced Neural Network Applications #CCD and CMOS Imaging Sensors #cs.AR #cs.LG #cs.PF #cs.PL #stat.ML
paper · pdf · doi:10.1109/socc.2017.8226056
openalex publication_date 2017/09/01 · arxiv published 2018/07/27 · arxiv updated 2018/07/27 · openalex created_date 2019/06/27 · openalex updated_date 2026/07/29
A deep-learning inference accelerator is synthesized from a C-language software program parallelized with Pthreads. The software implementation uses the well-known producer/consumer model with parallel threads interconnected by FIFO queues. The LegUp high-level synthesis (HLS) [1] tool synthesizes threads into parallel FPGA hardware, translating software parallelism into spatial parallelism. A complete system is generated where convolution, pooling and padding are realized in the synthesized accelerator, with remaining tasks executing on an embedded ARM processor. The accelerator incorporates reduced precision, and a novel approach for zero-weight-skipping in convolution. On a mid-sized Intel Arria 10 SoC FPGA, peak performance on VGG-16 is 138 effective GOPS.