2000/12/01 by A. Bakker, K. Thiele, Johan H. Huijsing · 1 citation
Engineering · #Analog and Mixed-Signal Circuit Design #Advancements in PLL and VCO Technologies #Advancements in Semiconductor Devices and Circuit Design
paper · doi:10.1109/4.890300
openalex publication_date 2000/12/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/06/22
A CMOS nested-chopper instrumentation amplifier is presented with a typical offset of 100 nV. This performance is obtained by nesting an additional low-frequency chopper pair around a conventional chopper amplifier. The inner chopper pair removes the 1/f noise, while the outer chopper pair reduces the residual offset. The test chip is free from 1/f noise and has a thermal noise of 27 nV//spl radic/Hz consuming a total supply current of 200 /spl mu/A.