2026/06/29 by Xiaotong Yuan
Computer Science · #cs.AR
arxiv created 2026/06/29 · arxiv updated 2026/08/04
Address interleaving balances bandwidth across caches, DRAM, and GPU partitions. In a multi-level interconnect topology, the mapping must be a one-to-one, invertible correspondence between logical and encoded addresses and, under typical access patterns, keep traffic uniform at every level's egress ports, not only at terminal slave nodes. Using random access as the stimulus and terminal uniformity as the acceptance criterion is insufficient for cascaded interconnects; this paper partitions workloads by access-pattern priority and requires a global bijection with no slave node left unvisited for extended periods. Per-level coefficient of variation (CV), consecutive same-port run length, and sliding-window peak occupancy evaluate traffic at each level's egress. HSRAI preserves high-order and intra-line low-order address bits and applies a W-bit bijection only to the intermediate index segment. Full-domain topologies use offline GF(2) affine search with matrix and salt parameters selected via priority-ranked access patterns and per-level admissibility hard constraints; pruned topologies combine the Chinese Remainder Theorem with remapping. Evaluation uses a reproducible C++ benchmark covering linear streams, matrix tiling, and 2D arithmetic lattices. On the 128-node full-domain topology, the proposed affine map satisfies bijection, terminal balance, design-time admissibility thresholds, and zero long-window starvation on the high-priority acceptance set; fixed XOR and folding/table baselines expose intermediate-level hotspots or extended zero-access periods. For pruned topologies, the CRT variant significantly improves per-level metrics on linear and tiling accesses. Artifact: https://github.com/xiaotongyuan/hsraiaddresshash (tag paper-v11).