2021/08/20 by Zuodong Zhang, Runsheng Wang, Xuguang Shen +5 · 2 citations
Engineering · #Advancements in Semiconductor Devices and Circuit Design #Algorithm #Circuit design #Circuit reliability #Computer science #Electronic design automation #Electronic engineering #Embedded system #Engineering #Integrated Circuits and Semiconductor Failure Analysis #Key (lock) #Logic gate #Margin (machine learning) #Reliability (semiconductor) #Reliability engineering #Scalability #Semiconductor materials and devices #Static timing analysis #Workload
paper · doi:10.1109/ted.2021.3096171
openalex publication_date 2021/08/20 · openalex created_date 2025/10/10 · openalex updated_date 2026/08/01
Due to severer transistor aging at nanoscale, circuit design margin becomes extremely tight for advanced technology nodes. Thus, reliability-aware circuit design is urgently needed. In this article, a new framework to perform aging-aware static timing analysis (STA) is presented for reliability analysis. The key parts of aging-aware STA flows are workload analysis and aged delay/transition calculation. For the workload analysis, a new analytical stress probability (SP) calculation model is proposed, which considers the floating effect and signal correlations. For aged delay/transition calculation, a new aging-aware model is developed, which is accessible to large industrial libraries. The results show that the proposed model achieves high accuracy in the degradation estimation and aged-path-delay calculation. Due to its high accuracy and scalability, the proposed framework is a promising solution that is compatible with commercial Electronic Design Automation (EDA) tools.