A Regular Layout for Parallel Adders

1982/03/01 by Brent, Kung · 14 citations
Computer Science · Engineering · #Numerical Methods and Algorithms #Low-power high-performance VLSI design #VLSI and FPGA Design Techniques

paper · doi:10.1109/tc.1982.1675982

Abstract

With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.

Cited by

• Prefix Sums via Kronecker Products
• Sliding Window Recurrences for Sequence Models
• PrefixGPT: Prefix Adder Optimization by a Generative Pre-trained Transformer
• A Fast Combined Decimal Adder/Subtractor
• Neural Shuffle-Exchange Networks -- Sequence Processing in O(n log n) Time
• Efficient numeracy in language models through single-token number embeddings
• A Near-Cache Architectural Framework for Cryptographic Computing
• Flock: Fast Proving for Batch Boolean Computations
• Smaller Circuits for Bit Addition
• NESTA: Hamming Weight Compression-Based Neural Proc. Engine
• A Higher radix architecture for quantum carry-lookahead adder. [europepmc]
• A scalable automated framework for multiply-accumulate unit design in high-performance computing applications. [europepmc]
• RandMScan: accelerating parallel scan via matrix computation and random-jump strategy. [europepmc]
• Automated and Scalable Verification of Integer Multipliers [europepmc]

Related

• On the Design and Analysis of Quaternary Serial and Parallel Adders
• Smaller Circuits for Bit Addition
• Optimal Final Carry Propagate Adder Design for Parallel Multipliers
• Binary Adder Circuits of Asymptotically Minimum Depth, Linear Size, and Fan-Out Two
• Faster Linear-Size And-Or Path and Adder Circuits