A Two's Complement Parallel Array Multiplication Algorithm

1973/12/01 by C.R. Baugh, B.A. Wooley · 4 citations
Computer Science · Engineering · #Interconnection Networks and Systems #Cellular Automata and Applications #Engineering and Test Systems

paper · doi:10.1109/t-c.1973.223648

Abstract

An algorithm for high-speed, two's complement, m-bit by n-bit parallel array multiplication is described. The two's complement multiplication is converted to an equivalent parallel array addition problem in which each partial product bit is the AND of a multiplier bit and a multiplicand bit, and the signs of all the partial product bits are positive.

Cited by

• AxOSyn: An Open-source Framework for Synthesizing Novel Approximate Arithmetic Operators
• On the use of inexact, pruned hardware in atmospheric modelling. [europepmc]
• Digital Circuit for Seamless Resampling ADC Output Streams. [europepmc]
• Automated and Scalable Verification of Integer Multipliers [europepmc]

Related

• Design of a Reformed Array Logic Binary Multiplier for High-Speed Computations
• Operand Folding Hardware Multipliers
• Fast multiplication by two's complement addition of numbers represented as a set of polynomial radix 2 indexes, stored as an integer list for massively parallel computation
• Faster truncated integer multiplication
• Parallel Integer Polynomial Multiplication