1993/03/01 by C.D. Walter, Colin D. Walter · 215 citations
Computer Science · Mathematics · #Advanced Data Storage Technologies #Algorithm #Arithmetic #Combinatorics #Computer science #Cryptography #Cryptography and Data Security #Cryptography and Residue Arithmetic #Cryptosystem #Embedded system #Latency (audio) #Mathematics #Modular arithmetic #Modular design #Multiplication (music) #Multiplication algorithm #Operating system #Parallel computing #Systolic array #Telecommunications #Very-large-scale integration
paper · doi:10.1109/12.210181
published in IEEE Transactions on Computers 42(3), 376-378 (Institute of Electrical and Electronics Engineers)
openalex publication_date 1993/03/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/29
A systolic array for modular multiplication is presented using the ideally suited algorithm of P.L. Montgomery (1985). Throughput is one modular multiplication every clock cycle, with a latency of 2n+2 cycles for multiplicands having n digits. Its main use would be where many consecutive multiplications are done, as in RSA cryptosystems.>