2026/07/30 by Arash Ghasemi
Computer Science · #cs.AR
arxiv created 2026/07/30 · arxiv updated 2026/07/31
This paper identifies a dynamical constraint on analog-computing approaches in which a row of the matrix is represented by an impedance network. It shows that the fastest normalized mode is no more than 2π times the largest combined unity-gain bandwidth (CUGBW) among all the circuit rows. The CUGBW of a row equals its finite-gain-adjusted unity-gain bandwidth plus the contributions of all rows coupled to it. Each contribution is the square root of the product of the two rows' unity-gain bandwidths multiplied by their coupling conductance and divided by the square root of the product of their total conductance loadings. This bound plays a role analogous to the Courant-number restriction in time-stepping methods by limiting the operator rates that analog hardware can physically represent and resolve at its outputs. The theory is validated using large-scale LTspice simulations across architectures ranging from CMOS to thermionic vacuum-tube circuits. The benchmark circuits implement a one-dimensional heat equation, a graph-based semi-supervised learning problem, and a graph-regularized regression.