2018/11/01 by Sahand Salamat, Mohsen Imani, Saransh Gupta +1 · 1 voice
Computer Science · Engineering · #Advanced Memory and Neural Computing #Ferroelectric and Negative Capacitance Devices #Parallel Computing and Optimization Techniques
paper · doi:10.1109/icrc.2018.8638592
openalex publication_date 2018/11/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/29
We live in a world where technological advances are continually creating more data than what we can deal with. Machine learning algorithms, in particular Deep Neural Networks (DNNs), are essential to process such large data. Computation of DNNs requires loading the trained network on the processing element and storing the result in memory. Therefore, running these applications need a high memory bandwidth. Traditional cores are memory limited in terms of the memory bandwidth. Hence, running DNNs on traditional cores results in high energy consumption and slows down processing speed due to a large amount of data movement between memory and processing units. Several prior works tried to address data movement issue by enabling Processing In-Memory (PIM)using crossbar analog multiplication. However, these designs suffer from the large overhead of data conversion between analog and digital domains. In this work, we propose RNSnet, which uses Residue Number System (RNS)to execute neural network completely in the digital domain in memory. RNSnet simplifies the fundamental neural network operations and maps them to in-memory addition and data access. We test the efficiency of the proposed design on several popular neural network applications. Our experimental result shows that RNSnet consumes 145.5× less energy and obtains 35.4× speedup as compared to NVIDIA GPU GTX 1080. In addition, our results show that RNSnet can achieve 8.5× higher energy-delay product as compared to the state-of-the-art neural network accelerators.