2015/05/31 by Benjamin A. Braun, Benjamin Braun, Braun, Benjamin A. +4 · 4 voices · 21 citations
Computer Science · #CPU cache #Cache #Cache algorithms #Cache invalidation #Code (set theory) #Computer network #Computer science #Computer security #Cryptographic Implementations and Security #Cryptography #Embedded system #Implementation #Operating system #Overhead (engineering) #Parallel computing #Physical Unclonable Functions (PUFs) and Hardware Security #Programming language #Security and Verification in Computing #Set (abstract data type) #Side channel attack #Timing attack #cs.CR
paper · pdf · doi:10.48550/arxiv.1506.00189
published in arXiv (Cornell University) (Cornell University) · 15 pages, 10 figures, submitted to NDSS 2016
openalex publication_date 2015/05/31 · arxiv created 2015/08/31 · arxiv updated 2015/09/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Timing and cache side channels provide powerful attacks against many sensitive operations including cryptographic implementations. Existing defenses cannot protect against all classes of such attacks without incurring prohibitive performance overhead. A popular strategy for defending against all classes of these attacks is to modify the implementation so that the timing and cache access patterns of every hardware instruction is independent of the secret inputs. However, this solution is architecture-specific, brittle, and difficult to get right. In this paper, we propose and evaluate a robust low-overhead technique for mitigating timing and cache channels. Our solution requires only minimal source code changes and works across multiple languages/platforms. We report the experimental results of applying our solution to protect several C, C++, and Java programs. Our results demonstrate that our solution successfully eliminates the timing and cache side-channel leaks while incurring significantly lower performance overhead than existing approaches.