1976/06/01 by J.F. Dickson, John F. Dickson · 11 citations
Engineering · #Advancements in Semiconductor Devices and Circuit Design #CMOS #Chip #Dropout voltage #Electrical engineering #Electrical impedance #Electronic circuit #Electronic engineering #Engineering #Frequency multiplier #Integrated circuit #Low-power high-performance VLSI design #Multiplier (economics) #Output impedance #Semiconductor materials and devices #Voltage #Voltage divider #Voltage multiplier
paper · doi:10.1109/jssc.1976.1050739
openalex publication_date 1976/06/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/29
An improved voltage multiplier technique has been developed for generating +40 V internally in p-channel MNOS integrated circuits to enable them to be operated from standard +5- and -12-V supply rails. With this technique, the multiplication efficiency and current driving capability are both independent of the number of multiplier stages. A mathematical model and simple equivalent circuit have been developed for the multiplier and the predicted performance agrees well with measured results. A multiplier has already been incorporated into a TTL compatible nonvolatile quad-latch, in which it occupies a chip area of 600 /spl mu/m/spl times/240 /spl mu/m. It is operated with a clock frequency of 1 MHz and can supply a maximum load current of about 10 /spl mu/A. The output impedance is 3.2 M/spl Omega/.