2008/12/01 by Kevin J. Wang, Ashok Swaminathan, Ian Galton
Engineering · #Advancements in PLL and VCO Technologies #Semiconductor Lasers and Optical Devices #Radio Frequency Integrated Circuit Design
paper · doi:10.1109/jssc.2008.2005716
This paper demonstrates that spurious tones in the output of a fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> PLL can be reduced by replacing the DeltaSigma modulator with a new type of digital quantizer and adding a charge pump offset combined with a sampled loop filter. It describes the underlying mechanisms of the spurious tones, proposes techniques that mitigate the effects of the mechanisms, and presents a phase noise cancelling 2.4 GHz ISM-band CMOS PLL that demonstrates the techniques. The PLL has a 975 kHz loop bandwidth and a 12 MHz reference. Its phase noise has a worst-case reference spur power of - 70 dBc and a worst-case in-band fractional spur power of -64 dBc.