Synchronous Mirror Delay for Multiphase Locking

2004/01/01 by Y.J. Yoon, Yong Jin Yoon, H.I. Kwon +5
Engineering · #Iterative Learning Control Systems #Thermal Analysis in Power Transmission #Semiconductor Lasers and Optical Devices

paper · doi:10.1109/jssc.2003.820871

Abstract

A clock generation circuit having the function of multiphase locking was designed using the synchronous mirror delay (SMD) scheme. The internal clock can be synchronized to the external clock with intended phase difference. The synchronizing error of the clock generation circuit is reduced below the delay time of unit delay stage by compensation characteristics of detecting circuit in SMD. A 32-M double data rate (DDR) SRAM including the clock generation circuit is fabricated using 0.13-/spl mu/m CMOS technology. To measure the synchronizing error of the clock generation circuit, the test elements group (TEG) system is designed and fabricated with the main system. The synchronizing error of the clock generation circuit is far smaller than the delay time of unit delay stage at zero phase locking and similar to the delay time of unit delay stage at multiphase locking.

Citations

• A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay

Related

• A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay
• A Clock Synchronizer for Repeaterless Low Swing On-Chip Links
• A high precision TDC based on a multi-phase clock
• A 3.8 ps RMS time synchronization implemented in a 20 nm FPGA
• A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips