2009/03/24 by Matthew Z. Straayer, Michael H. Perrott · 5 citations
Engineering · #Advancements in PLL and VCO Technologies #Analog and Mixed-Signal Circuit Design #Photonic and Optical Devices
paper · doi:10.1109/jssc.2009.2014709
An 11-bit, 50-MS/s time-to-digital converter (TDC) using a multipath gated ring oscillator with 6 ps of effective delay per stage demonstrates 1st-order noise shaping. At frequencies below 1 MHz, the TDC error integrates to 80 fs (rms) for a dynamic range of 95 dB with no calibration required. The 157 times 258 mum TDC is realized in 0.13 mum CMOS and, depending on the time difference between input edges, consumes 2.2 to 21 mA from a 1.5 V supply.