2016/02/15 by Ting-Kuei Kuan, Shen-Iuan Liu · 1 citation
Engineering · #Advancements in PLL and VCO Technologies #Radio Frequency Integrated Circuit Design #Photonic and Optical Devices
paper · doi:10.1109/jssc.2016.2519391
This paper presents a digital bang-bang phase-locked loop (DBPLL) that employs automatic loop gain control and loop latency reduction techniques to enhance the jitter performance. Due to noise filtering properties, a DBPLL has an optimal loop gain which gives rise to the best jitter performance, taking into account external and internal noise sources. By using the automatic loop gain control technique, the DBPLL can automatically attain this loop gain in background to minimize the jitter. This paper also exploits time-series analysis to analyze the DBPLL. In particular, the closed-form gain of a bang-bang phase detector (BBPD) is first derived, taking into account reference clock noise and oscillator noise simultaneously. The chip was fabricated in a 40 nm CMOS process. This DBPLL achieves <; 290 fs integrated rms jitter and <;- 72.89 dBc reference spurs. It consumes 3.8 mW from a 1.1 V supply while operating at 3.96 GHz. This translates to an figure-of-merit (FOM) of -245 dB.