GoGoTB: Agentic RTL Verification with Specification-Grounded Coverage Closure

2026/07/28 by Xin Xin, Jincheng Lou, Junhui Li +11
Computer Science · #cs.AI

paper · pdf

9 pages, 7 figures, 3 tables. Xin Xin and Jincheng Lou contributed equally to this work and share first authorship

arxiv created 2026/07/28 · arxiv updated 2026/07/30

Abstract

Functional verification dominates integrated circuit (IC) front-end engineering effort, and a single missed bug that escapes to silicon can trigger a costly respin. Recent large language models (LLMs) offer new opportunities to automate this process, yet existing LLM-based approaches generate each component through independent single-turn calls with no shared context, leaving interface mismatches undetected and reported coverage disconnected from specification requirements. To address these challenges, we present GoGoTB, an agentic framework that achieves end-to-end verification closure through three subsystems: an agentic execution control layer, an evolvable knowledge system, and specification-grounded coverage closure. The execution control layer separates deterministic enforcement from LLM reasoning at every tool and stage boundary. The knowledge system dispatches methodology and design-specific expertise on demand. The coverage framework anchors every bin to a named specification behavior so that each residual gap has a diagnosable root cause and a targeted remedy. Tested on 8 register transfer level (RTL) designs without any human intervention, GoGoTB achieves 100% environment generation success and averages 98.4% line, 97.2% branch, 97.0% toggle, and 83.2% functional coverage. No prior work successfully generates a complete verification environment or achieves meaningful coverage on the same benchmarks.

Citations

• Spec2Assertion: Automatic Pre-RTL Assertion Generation using Large Language Models with Progressive Regularization
• From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification
• UVLLM: An Automated Universal RTL Verification Framework using LLMs
• CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design
• AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design
• AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
• Using LLMs to Facilitate Formal Verification of RTL
• Reflexion: Language Agents with Verbal Reinforcement Learning

Related

• PRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verification
• AIvril: AI-Driven RTL Generation With Verification In-The-Loop
• UVLLM: An Automated Universal RTL Verification Framework using LLMs
• From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification
• Faver: Boosting LLM-based RTL Generation with Function Abstracted Verifiable Middleware