2015/10/16 by Hsuan-Yu Chang, Ching-Yuan Yang, Ching‐Yuan Yang
Engineering · #Advancements in PLL and VCO Technologies #Advancements in Semiconductor Devices and Circuit Design #Analog and Mixed-Signal Circuit Design
paper · doi:10.1109/tvlsi.2015.2478835
openalex publication_date 2015/10/16 · openalex created_date 2025/10/10 · openalex updated_date 2026/06/26
A 6-bit flash analog-to-digital converter (ADC) using reference-voltage-interpolated calibration to improve linearity and reduce power dissipation is presented. In the ADC, the digital calibration logic employs the successive approximation algorithm and the minimized residue algorithm to determine precise calibration levels. Implemented by a 90-nm CMOS process, the proposed ADC can achieve a signal-to-noise-and-distortion ratio of 36 dB for a low input frequency and 33.5 dB for a Nyquist-rate input frequency at a 2-GS/s sampling rate. The peaks of integral and differential nonlinearities after calibration are 0.36 and 0.42 least significant bit, respectively. The power consumption is 25 mW at 2 GS/s from a 1.2 V supply. The core area is 0.32 mm × 0.62 mm, and the figure of merit is 0.34 pJ/conversion step.