Leakage control with efficient use of transistor stacks in single threshold CMOS

2002/02/01 by Mark C. Johnson, M.C. Johnson, Dinesh Somasekhar +5 · 1 citation
Engineering · #Advancements in Semiconductor Devices and Circuit Design #Low-power high-performance VLSI design #Radiation Effects in Electronics

paper · doi:10.1109/92.988724

openalex publication_date 2002/02/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/30

Abstract

The state dependence of leakage can be exploited to obtain modest leakage savings in complementary metal-oxide-semiconductor (CMOS) circuits. However, one can modify circuits considering state dependence and achieve larger savings. We identify a low-leakage state and insert leakage-control transistors only where needed. Leakage levels are on the order of 35% to 90% lower than those obtained by state dependence alone. Using a modified standard-cell-design flow, area overhead for combinational logic was found to be on the order of 18%. The proposed technique minimizes performance impact, does not require multiple-threshold voltages, and supports a standard-cell-design flow.

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• LECTOR: a technique for leakage reduction in CMOS circuits

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