A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing

2012/01/31 by Anh Tuan, Anh-Tuan Do, Shoushun Chen +3 · 2 citations
Computer Science · Engineering · #Advanced Memory and Neural Computing #Ferroelectric and Negative Capacitance Devices #Network Packet Processing and Optimization

paper · doi:10.1109/tvlsi.2011.2178276

openalex publication_date 2012/01/31 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/29

Abstract

Content addressable memory (CAM) offers high-speed search function in a single clock cycle. Due to its parallel match-line (ML) comparison, CAM is power-hungry. Thus, robust, high-speed and low-powerMLsense amplifiers are highly sought-after in CAM designs. In this paper, we introduce a parity bit that leads to 39% sensing delay reduction at a cost of less than 1% area and power overhead. Furthermore, we propose an effective gated-power technique to reduce the peak and average power consumption and enhance the robustness of the design against process variations. A feedback loop is employed to auto-turn off the power supply to the comparison elements and hence reduce the average power consumption by 64%. The proposed design can work at a supply voltage down to 0.5 V.

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• Precharge-Free, Low-Power Content-Addressable Memory
• Selective Match-Line Energizer Content Addressable Memory(SMLE -CAM)

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