ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping

2000/08/01 by Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
Computer Science · Engineering · #Embedded Systems Design Techniques #VLSI and Analog Circuit Testing #VLSI and FPGA Design Techniques

paper · doi:10.1109/92.863618

openalex publication_date 2000/08/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/06/26

Abstract

In this paper, we propose an iterative area/performance tradeoff algorithm for look-up table (LUT)-based field programmable gate array (FPGA) technology mapping. First, it finds an area-optimized, performance-considered initial network by a modified area optimization technique. Then, an iterative algorithm consisting of several resynthesizing techniques is applied to trade the area for the performance in the network gracefully. Experimental results show that this approach can efficiently provide a complete set of mapping solutions from the area-optimized one to the performance-optimized one for the given design. Furthermore, these two extreme solutions produced by our algorithm outperform the results provided by most existing algorithms. Therefore, our algorithm is very useful for the timing-driven, LUT-based FPGA synthesis.

Related

• Fast Iterative Dual-Output-Aware LUT Mapping for Fracturable FPGA Architectures
• Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper
• Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs
• Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage
• LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line Minimization