2021/07/29 by Andreas Abel, Jan Reineke · 4 voices · 2 citations
Computer Science · Engineering · #Advanced Data Storage Technologies #Parallel Computing and Optimization Techniques #Semiconductor materials and devices #cs.PF
paper · pdf · doi:10.1145/3524059.3532396
openalex publication_date 2022/06/16 · openalex created_date 2022/06/17 · openalex updated_date 2026/07/30
Performance models that statically predict the steady-state throughput of basic blocks on particular microarchitectures, such as IACA, Ithemal, llvm-mca, OSACA, or CQA, can guide optimizing compilers and aid manual software optimization. However, their utility heavily depends on the accuracy of their predictions. The average error of existing models compared to measurements on the actual hardware has been shown to lie between 9% and 36%. But how good is this? To answer this question, we propose an extremely simple analytical throughput model that may serve as a baseline. Surprisingly, this model is already competitive with the state of the art, indicating that there is significant potential for improvement.