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Electrical Degradation and Trapped Charge Evolution in SiC MOSFETs Under Power-Cycling Stress

2026/05/25 by Shijie Pan, Shanhai Gu, Shiwei Feng +8
Engineering · #Advancements in Semiconductor Devices and Circuit Design #Semiconductor materials and devices #Silicon Carbide Semiconductor Technologies

paper · doi:10.1109/tpel.2026.3696424

openalex publication_date 2026/05/25 · openalex created_date 2026/05/26 · openalex updated_date 2026/07/30

Abstract

The reliability of SiC MOSFETs under repetitive power cycling is a critical concern for power converter design. This work investigates the degradation behavior in SiC MOSFETs under power-cycling stress, and the trap analysis is carried out based on transient current method. Five samples are stressed under forward conduction with load current from 52.5 to 73.2 A. An inverse relationship is observed between the applied current and the number of cycles, determined by a 5% increase in the on-state voltage under hot conditions. Post-stress electrical characterizations reveal the positive threshold voltage shift and increased drain leakage current, with the degradation being more pronounced with an increasing number of cycles. Based on the actual transient current variations of samples, the trapping behaviors governed by exponential decay are extracted using Bayesian deconvolution. Three trap levels are identified with increased amplitudes under larger cycle count, and the activation energies are almost unchanged after power-cycling by the temperature-dependent measurements. It can be attributed to the increase in traps near the SiC/SiO2interface and within the gate oxide especially under higher cycle count. By directly linking macroscopic degradation to the evolution of microscopic traps, it provides profound insights for the reliability assessment of SiC MOSFETs in power electronic systems.

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