Low–Frequency Noise in Vertically Stacked Si n–Channel Nanosheet FETs

2020/01/20 by Alberto Vinícius de Oliveira, Alberto V. de Oliveira, Anabela Veloso +4 · 1 citation
Engineering · #Advancements in Semiconductor Devices and Circuit Design #Integrated Circuits and Semiconductor Failure Analysis #Semiconductor materials and devices

paper · doi:10.1109/led.2020.2968093

openalex publication_date 2020/01/20 · openalex created_date 2020/01/30 · openalex updated_date 2026/07/02

Abstract

This manuscript presents a systematic low-frequency noise analysis of inversion-mode vertically stacked silicon n-channel nanosheet MOSFETs on bulk wafers. Flicker noise due to carrier number fluctuations is shown as the dominant noise source, which is in line with previous reported studies on gate-all-around (GAA) nanowire nMOSFETs. In addition, the benchmark points out that the vertical stacking approach does not deteriorate the oxide trap density, since its normalized input-referred voltage noise Power Spectral Density at flat-band is lower compared to the data on non-stacked horizontal nanowire nMOSFETs. Another finding is that the Coulomb scattering mechanism dominates the mobility.

Citations

• 1/ƒ noise is no surface effect

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