Architecture and FPGA Implementation of Digital Time-to-Digital Converter for Sensing Applications

2025/08/12 by Zeinab Hijazi, Hijazi, Zeinab, Fatima Bzeih +3
Computer Science · Engineering · #Advancements in PLL and VCO Technologies #Analog and Mixed-Signal Circuit Design #FOS: Electrical engineering #Network Time Synchronization Technologies #Systems and Control (eess.SY) #electronic engineering #information engineering

paper · pdf · doi:10.48550/arxiv.2508.08725

openalex publication_date 2025/08/12 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

Many application domains face the challenges of high-power consumption and high computational demands, especially with the advancement in embedded machine learning and edge computing. Designing application-specific circuits is crucial to reducing hardware complexity and power consumption. In these perspectives, this paper presents the design of a Digital Time-to-Digital converter (DTDC) based on multiple delay line topologies. The DTDC is implemented in VHDL for the Xilinx Artix-7 AC701 FPGA device. Simulation results demonstrate the effectiveness of the circuit in converting the input period along a wide range up to 1ps. The designed circuit is implemented with less than 1% of the resource utilization on the target FPGA device.

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