2018/05/09 by Duc-Phuc Nguyen, Dinh-Dung Le, Nguyen, Duc-Phuc +7 · 1 citation
Engineering · #FOS: Electrical engineering #Signal Processing (eess.SP) #eess.SP #electronic engineering #information engineering
paper · pdf · doi:10.48550/arxiv.1805.03398
Being reviewd by EURASIP Journal of Wireless Communication and Networking
arxiv created 2018/05/09 · arxiv updated 2018/05/10
In this paper, we introduce a couple of hardware implementations of compact VLC transmitter and receiver for the first time. Compared with related works, our VLC transmitter is non-RLL one, that means flicker mitigation can be guaranteed even without RLL codes. In particular, we have utilized a centralized bit probability distribution of a prescrambler and a Polar encoder to create a non-RLL flicker mitigation solution. Moreover, at the receiver, a 3-bit soft-decision filter is proposed to analyze signals received from real VLC channel to extract log-likelihood ratio (LLR) values and feed them to the FEC decoder. Therefore, soft-decoding of Polar decoder can be implemented to improve the bit-error-rate (BER) performance of the VLC system. Finally, we introduce a novel very large scale integration (VLSI) architecture for the compact VLC transmitter and receiver; and synthesis our design under FPGA/ASIC synthesis tools. Due to the non-RLL basic, our system has an evidently good code-rate and a reduced-complexity compared with other RLL-based receiver works. Also, we present FPGA and ASIC synthesis results of the proposed architecture with evaluations of power consumption, area, energy-per-bits and so on.