2018/07/30 by Tzyy Juin Kao, Kao, Tzyy-Juin, Wolfgang Fink +1
Computer Science · Engineering · #Distributed #Embedded Systems Design Techniques #Emerging Technologies (cs.ET) #FOS: Computer and information sciences #Interconnection Networks and Systems #Networking and Internet Architecture (cs.NI) #Parallel #Performance (cs.PF) #VLSI and FPGA Design Techniques #and Cluster Computing (cs.DC)
paper · pdf · doi:10.48550/arxiv.1807.11607
openalex publication_date 2018/07/30 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
With the advent of multi-core processors, network-on-chip design has been key in addressing network performances, such as bandwidth, power consumption, and communication delays when dealing with on-chip communication between the increasing number of processor cores. As the numbers of cores increase, network design becomes more complex. Therefore, there is a critical need in soliciting computer aid in determining network configurations that afford optimal performance given resources and design constraints. We propose a Pareto-optimization framework that explores the space of possible network configurations to determine optimal network latencies, power consumption, and the corresponding link allocations. For a given number of routers, average network latency and power consumption as example performance objectives can be displayed in form of Pareto-optimal fronts, thus not only offering a design tool, but also enabling trade-off studies.