2024/12/29 by Francesco Conti, Angelo Garofalo, Conti, Francesco +7 · 1 citation
Computer Science · Engineering · #CCD and CMOS Imaging Sensors #Embedded Systems Design Techniques #FOS: Computer and information sciences #FOS: Electrical engineering #Hardware Architecture (cs.AR) #Neural and Evolutionary Computing (cs.NE) #Parallel Computing and Optimization Techniques #Signal Processing (eess.SP) #electronic engineering #information engineering
paper · pdf · doi:10.48550/arxiv.2412.20391
openalex publication_date 2024/12/29 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Since 2013, the PULP (Parallel Ultra-Low Power) Platform project has been one of the most active and successful initiatives in designing research IPs and releasing them as open-source. Its portfolio now ranges from processor cores to network-on-chips, peripherals, SoC templates, and full hardware accelerators. In this article, we focus on the PULP experience designing heterogeneous AI acceleration SoCs - an endeavour encompassing SoC architecture definition; development, verification, and integration of acceleration IPs; front- and back-end VLSI design; testing; development of AI deployment software.