2020/09/11 by Jonathan Ling, Ling, Jonathan, Paul Cautereels +1
Computer Science · Engineering · #Advanced Wireless Communication Technologies #Cooperative Communication and Network Coding #Error Correcting Code Techniques #FOS: Computer and information sciences #FOS: Electrical engineering #Networking and Internet Architecture (cs.NI) #Signal Processing (eess.SP) #electronic engineering #information engineering
paper · pdf · doi:10.48550/arxiv.2009.05534
openalex publication_date 2020/09/11 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
The GPU as a digital signal processing accelerator for cloud RAN is investigated. A new design for a 5G NR low density parity check code decoder running on a GPU is presented. The algorithm is flexibly adaptable to GPU architecture to achieve high resource utilization as well as low latency. It improves over an existing layered design that processes additional codewords in parallel to increase utilization. In comparison to a decoder implemented on a FPGA (757K gate), the new GPU (24 core) decoder has 3X higher throughput. The GPU decoder exhibits 3 to 5X lower decoding power efficiency, as typical of a general-purpose processor. Thus, GPUs may find application as cloud accelerators where rapid deployment and flexibility are prioritized over decoding power efficiency.