2007/01/01 by Matthias Grumer, Grumer, Matthias, M. Wendt +8
Computer Science · Engineering · #Embedded Systems Design Techniques #Green IT and Sustainability #Parallel Computing and Optimization Techniques #Software power optimization #compiler optimization #peak reduction
paper · doi:10.4230/dagsemproc.07041.5
openalex publication_date 2007/01/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
RF-powered smart cards are widely used in different application areas today. For smart cards not only performance is an important attribute, but also the power consumed by a given application. The power consumed is heavily depending on the software executed on the system. The power profile, especially the power peaks, of an executed application influence the system stability and security. Flattening the power profile can thus increase the stability and security of a system. In this paper we present an optimization system that allows a reduction of power peaks based on a compiler optimization. The optimizations are done on different levels of the compiler. In the backend of the compiler we present new instruction scheduling algorithms. On the intermediate language level we propose the use of iterative compiling for reducing critical peaks.