2021/12/13 by Lennart Bamberg, Bamberg, Lennart, Arash Pourtaherian +7 · 1 citation
Engineering · #Advanced Memory and Neural Computing #Artificial Intelligence (cs.AI) #CCD and CMOS Imaging Sensors #FOS: Computer and information sciences #Ferroelectric and Negative Capacitance Devices #Hardware Architecture (cs.AR)
paper · pdf · doi:10.48550/arxiv.2112.07019
openalex publication_date 2021/12/13 · openalex created_date 2025/10/10 · openalex updated_date 2026/08/01
Manufacturing-viable neuromorphic chips require novel computer architectures to achieve the massively parallel and efficient information processing the brain supports so effortlessly. Emerging event-based architectures are making this dream a reality. However, the large memory requirements for synaptic connectivity are a showstopper for the execution of modern convolutional neural networks (CNNs) on massively parallel, event-based (spiking) architectures. This work overcomes this roadblock by contributing a lightweight hardware scheme to compress the synaptic memory requirements by several thousand times, enabling the execution of complex CNNs on a single chip of small form factor. A silicon implementation in a 12-nm technology shows that the technique increases the system's implementation cost by only 2%, despite achieving a total memory-footprint reduction of up to 374x compared to the best previously published technique.