2022/08/11 by Yosuke Ueno, Masaaki Kondo, Ueno, Yosuke +7 · 2 citations
Computer Science · Engineering · #FOS: Computer and information sciences #FOS: Physical sciences #Ferroelectric and Negative Capacitance Devices #Hardware Architecture (cs.AR) #Quantum Computing Algorithms and Architecture #Quantum Physics (quant-ph) #Semiconductor materials and devices
paper · pdf · doi:10.48550/arxiv.2208.05758
openalex publication_date 2022/08/11 · openalex created_date 2022/08/13 · openalex updated_date 2026/07/28
Quantum error correction (QEC) is essential for quantum computing to mitigate the effect of errors on qubits, and surface code (SC) is one of the most promising QEC methods. Decoding SCs is the most computational expensive task in the control device of quantum computers (QCs), and many works focus on accurate decoding algorithms for SCs, including ones with neural networks (NNs). Practical QCs also require low-latency decoding because slow decoding leads to the accumulation of errors on qubits, resulting in logical failures. For QCs with superconducting qubits, a practical decoder must be very power-efficient in addition to having high accuracy and low latency. In order to reduce the hardware complexity of QC, we are supposed to decode SCs in a cryogenic environment with a limited power budget, where superconducting qubits operate. In this paper, we propose an NN-based accurate, fast, and low-power decoder capable of decoding SCs and lattice surgery (LS) operations with measurement errors on ancillary qubits. To achieve both accuracy and hardware efficiency of the SC decoder, we apply a binarized NN. We design a neural processing unit (NPU) for the decoder with SFQ-based digital circuits and evaluate it with a SPICE-level simulation. We evaluate the decoder performance by a quantum error simulator for the single logical qubit protection and the minimum operation of LS with code distances up to 13, and it achieves 2.5% and 1.0% accuracy thresholds, respectively.