2014/10/21 by Tareq B. Malas, Tareq Malas, Malas, Tareq +7
Computer Science · Engineering · #Advanced Memory and Neural Computing #FOS: Computer and information sciences #Parallel Computing and Optimization Techniques #Performance (cs.PF) #Semiconductor materials and devices #cs.PF
paper · pdf · doi:10.48550/arxiv.1410.5561
arxiv created 2014/10/21 · openalex publication_date 2014/10/21 · arxiv updated 2014/10/22 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
We study the impact of tunable parameters on computational intensity (i.e., inverse code balance) and energy consumption of multicore-optimized wavefront diamond temporal blocking (MWD) applied to different stencil-based update schemes. MWD combines the concepts of diamond tiling and multicore-aware wavefront blocking in order to achieve lower cache size requirements than standard single-core wavefront temporal blocking. We analyze the impact of the cache block size on the theoretical and observed code balance, introduce loop tiling in the leading dimension to widen the range of applicable diamond sizes, and show performance results on a contemporary Intel CPU. The impact of code balance on power dissipation on the CPU and in the DRAM is investigated and shows that DRAM power is a decisive factor for energy consumption, which is strongly influenced by the code balance. Furthermore we show that highest performance does not necessarily lead to lowest energy even if the clock speed is fixed.