2019/11/19 by Fabian Schuiki, Schuiki, Fabian, Florian Zaruba +5 · 2 voices · 4 citations
Computer Science · #Advanced Data Storage Technologies #Distributed #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Interconnection Networks and Systems #Parallel #Parallel Computing and Optimization Techniques #and Cluster Computing (cs.DC) #cs.AR #cs.DC
paper · pdf · doi:10.48550/arxiv.1911.08356
openalex publication_date 2019/11/19 · arxiv published 2019/11/19 · arxiv updated 2020/04/01 · openalex created_date 2022/07/26 · openalex updated_date 2026/07/28
Single-issue processor cores are very energy efficient but suffer from the\nvon Neumann bottleneck, in that they must explicitly fetch and issue the\nloads/storse necessary to feed their ALU/FPU. Each instruction spent on moving\ndata is a cycle not spent on computation, limiting ALU/FPU utilization to 33%\non reductions. We propose "Stream Semantic Registers" to boost utilization and\nincrease energy efficiency. SSR is a lightweight, non-invasive RISC-V ISA\nextension which implicitly encodes memory accesses as register reads/writes,\neliminating a large number of loads/stores. We implement the proposed extension\nin the RTL of an existing multi-core cluster and synthesize the design for a\nmodern 22nm technology. Our extension provides a significant, 2x to 5x,\narchitectural speedup across different kernels at a small 11% increase in core\narea. Sequential code runs 3x faster on a single core, and 3x fewer cores are\nneeded in a cluster to achieve the same performance. The utilization increase\nto almost 100% in leads to a 2x energy efficiency improvement in a multi-core\ncluster. The extension reduces instruction fetches by up to 3.5x and\ninstruction cache power consumption by up to 5.6x. Compilers can automatically\nmap loop nests to SSRs, making the changes transparent to the programmer.\n