2021/08/17 by Lucas Moura Santana, Santana, Lucas Moura, Duarte L. Oliveira +3
Computer Science · Engineering · Medicine · #Analog and Mixed-Signal Circuit Design #CCD and CMOS Imaging Sensors #ECG Monitoring and Analysis #FOS: Electrical engineering #Sensor Technology and Measurement Systems #Signal Processing (eess.SP) #electronic engineering #information engineering
paper · pdf · doi:10.48550/arxiv.2108.07564
openalex publication_date 2021/08/17 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
The ubiquitous use of sensing and signal processing is increasing\nexponentially with the advance of the Internet of Everything (IoE). In this\ncontext, the design of every time more power efficient sensor nodes is a must.\nWithin these nodes, one of the most power-hungry components are the\nanalog-to-digital converters (ADC). These components are used everywhere to\ntranslate real-world analog signals into computer intelligible digital signals.\nOne of the promising architecture for the sensing of physiological signals is\nthe level crossing ADC due to the sparse characteristics of those signals. One\nof the challenges to improve the power efficiency of this type of ADC lies in\nthe use of continuous comparators to keep track of the input signal within the\nvoltage references. The aim of this work is to investigate the impact of using\ncontinuous comparator which can be turned off without incurring error to the\nconversion of the level crossing ADC. New boundaries will be set for the\ncorrect behavior of the level crossing ADC together with the conditions for\npower saving with the proposed architecture. A 1V 5-bits level crossing ADC was\nimplemented using the TSMC 0.18um process and fabricated for laboratory\nmeasurements. The ADC consumes 12.2uW during tracking state and with the\nproposed technique, the reduction of the average power can go from 4.2% to\n45.5% depending on the activity and the type of the input signal.\n