2022/09/24 by M. Yassine Naghmouchi, Naghmouchi, M. Yassine, Shoushou Ren +7
Computer Science · #FOS: Computer and information sciences #Interconnection Networks and Systems #Network Time Synchronization Technologies #Networking and Internet Architecture (cs.NI) #Software-Defined Networks and 5G
paper · pdf · doi:10.48550/arxiv.2209.12052
openalex publication_date 2022/09/24 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
With 5G networking, deterministic guarantees are emerging as a key enabler. In this context, we present a scalable Damper-based architecture for Large-scale Deterministic IP Networks (D-LDN) that meets required bounds on end-to-end delay and jitter. This work extends the original LDN architecture, where flows are shaped at ingress gateways and scheduled for transmission at each link using an asynchronous and cyclic opening of gate-controlled queues. To further relax the need for clock synchronization between devices, we use dampers, that consist in jitter regulators, to control the burstiness flows to provide a constant target delay at each hop. We introduce in details how data plane functionalities are implemented at all nodes (gateways and core) and we derive how the end-to-end delay and jitter are calculated. For the control plane, we propose a column generation algorithm to quickly take admission control decisions and maximize the accepted throughput. For a set of flows, it determines acceptance and selects the best shaping and routing policy. Through a proof-of-concept implementation in simulation, we verify that the architecture meets promised guarantees and that the control plane can operate efficiently at large-scale.