2015/01/05 by Stephan Held, Held, Stephan, Nicolas Kämmerling +1
Computer Science · Engineering · #Computational Geometry (cs.CG) #FOS: Computer and information sciences #Low-power high-performance VLSI design #VLSI and Analog Circuit Testing #VLSI and FPGA Design Techniques #cs.CG
paper · pdf · doi:10.48550/arxiv.1501.00933
openalex publication_date 2015/01/05 · arxiv created 2015/04/10 · arxiv updated 2015/04/13 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Given a set P of terminals in the plane and a partition of P into k subsets P1, ..., Pk, a two-level rectilinear Steiner tree consists of a rectilinear Steiner tree Ti connecting the terminals in each set Pi (i=1,...,k) and a top-level tree Ttop connecting the trees T1, ..., Tk. The goal is to minimize the total length of all trees. This problem arises naturally in the design of low-power physical implementations of parity functions on a computer chip. For bounded k we present a polynomial time approximation scheme (PTAS) that is based on Arora's PTAS for rectilinear Steiner trees after lifting each partition into an extra dimension. For the general case we propose an algorithm that predetermines a connection point for each Ti and Ttop (i=1,...,k). Then, we apply any approximation algorithm for minimum rectilinear Steiner trees in the plane to compute each Ti and Ttop independently. This gives us a 2.37-factor approximation with a running time of O(|P|log|P|) suitable for fast practical computations. The approximation factor reduces to 1.63 by applying Arora's approximation scheme in the plane.