2021/07/04 by Rayudu, Venkata Suresh, Kim, Ki Yong, Gharpurey, Ranjit
#FOS: Electrical engineering #Signal Processing (eess.SP) #electronic engineering #information engineering
paper · doi:10.48550/arxiv.2107.01535
A downconversion receiver employing a switch-based N-path filter with reduced harmonic response around the third- and fifth- LO harmonics is presented. The N-path filter is placed in a frequency-translation feedback loop that is effective at the 3rd and the 5th LO harmonics to mitigate harmonic downconversion. A pulse-width-modulated LO (PWM-LO) clocking scheme is used in the feedback upconverter to reduce the noise injected around the LO harmonic at the input of N-path downconverter. The compression resulting from blockers around the 3rd and the 5th LO harmonics is also suppressed as a result of reduced harmonic response. Compensation of peak frequency shift of the N-path response due to parasitic input capacitance is also described.