2020/09/11 by Zhewei Jiang, Jiangyi Li, Jiang, Zhewei +15
Neuroscience · #EEG and Brain-Computer Interfaces #FOS: Electrical engineering #Neural dynamics and brain function #Neuroscience and Neural Engineering #Signal Processing (eess.SP) #electronic engineering #information engineering
paper · pdf · doi:10.48550/arxiv.2009.05210
openalex publication_date 2020/09/11 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
This paper presents microwatt end-to-end neural signal processing hardware for deployment-stage real-time upper-limb movement intent decoding. This module features intercellular spike detection, sorting, and decoding operations for a 96-channel prosthetic implant. We design the algorithms for those operations to achieve minimal computation complexity while matching or advancing the accuracy of state-of-art Brain-Computer-Interface sorting and movement decoding. Based on those algorithms, we devise the architect of the neural signal processing hardware with the focus on hardware reuse and event-driven operation. The design achieves among the highest levels of integration, reducing wireless data rate by more than four orders of magnitude. The chip prototype in a 180-nm high-VTH, achieving the lowest power dissipation of 0.61 uW for 96 channels, 21X lower than the prior art at a comparable/better accuracy even with integration of kinematic state estimation computation.