2023/07/21 by Reza Asrar Ghaderloo, Yidi Shen, Ghaderloo, Reza Asrar +7
Engineering · #Advanced DC-DC Converters #FOS: Electrical engineering #Multilevel Inverters and Converters #Silicon Carbide Semiconductor Technologies #Systems and Control (eess.SY) #electronic engineering #information engineering
paper · pdf · doi:10.48550/arxiv.2307.11868
openalex publication_date 2023/07/21 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Bus-clamping Pulse Width Modulation (PWM) is an effective method to reduce the switching loss in a three-phase voltage source inverter (VSI). In bus-clamping PWM scheme, the phase legs are switched using high frequency PWM signals for two-third of the line cycle, while for the remaining duration of cycle, the pole voltage is clamped to either positive or negative rail of the DC bus. In PWM operation of a half bridge, a dead-time is applied between the gate signals of complementary switches to ensure safe and reliable operation. However, introduction of dead-time leads to poor power quality, increased Total Harmonic Distortion (THD) and variation in actual voltage compared to the intended pole voltage. Moreover, when the bus-clamping technique is used, the PWM has both high frequency switching region and clamped region in a line cycle, and consequently, the undesired effects of dead-time are further aggravated. Therefore, in order to enhance the quality of output voltage, this paper presents a dead-time compensation strategy for a VSI operating with bus-clamping PWM. The proposed method calculates the required compensation term to be added on the modulation signal considering wide range of operating conditions. Additionally, the compensation includes a new strategy for low current conditions near zero-crossing to avoid distortion. The proposed method is verified by simulation and experiments in a three-phase VSI with a switching frequency of 100 kHz and a fundamental frequency of 60Hz.