Analysis of Intel's Haswell Microarchitecture Using The ECM Model and Microbenchmarks

2015/11/11 by Hofmann, Johannes, Fey, Dietmar, Eitzinger, Jan +2
#Distributed #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Parallel #and Cluster Computing (cs.DC)

paper · doi:10.48550/arxiv.1511.03639

Abstract

This paper presents an in-depth analysis of Intel's Haswell microarchitecture for streaming loop kernels. Among the new features examined is the dual-ring Uncore design, Cluster-on-Die mode, Uncore Frequency Scaling, core improvements as new and improved execution units, as well as improvements throughout the memory hierarchy. The Execution-Cache-Memory diagnostic performance model is used together with a generic set of microbenchmarks to quantify the efficiency of the microarchitecture. The set of microbenchmarks is chosen such that it can serve as a blueprint for other streaming loop kernels.

Related

• Execution-Cache-Memory Performance Model: Introduction and Validation
• Introducing a Performance Model for Bandwidth-Limited Loop Kernels
• An analysis of core- and chip-level architectural features in four generations of Intel server processors
• An ECM-based energy-efficiency optimization approach for bandwidth-limited streaming kernels on recent Intel Xeon processors
• Microarchitectural comparison and in-core modeling of state-of-the-art CPUs: Grace, Sapphire Rapids, and Genoa