2025/06/10 by Mukul Lokhande, Lokhande, Mukul, Santosh Kumar Vishvakarma +1 · 3 citations
Computer Science · #Advanced Neural Network Applications #Artificial Intelligence (cs.AI) #Computational Complexity (cs.CC) #Embedded Systems Design Techniques #FOS: Computer and information sciences #FOS: Electrical engineering #Hardware Architecture (cs.AR) #Image and Video Processing (eess.IV) #Parallel Computing and Optimization Techniques #electronic engineering #information engineering
paper · pdf · doi:10.48550/arxiv.2506.08785
openalex publication_date 2025/06/10 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
The increasing complexity of AI models requires flexible hardware capable of supporting diverse precision formats, particularly for energy-constrained edge platforms. This work presents PARV-CE, a SIMD-enabled, multi-precision MAC engine that performs efficient multiply-accumulate operations using a unified data-path for 4/8/16-bit fixed-point, floating point, and posit formats. The architecture incorporates a layer adaptive precision strategy to align computational accuracy with workload sensitivity, optimizing both performance and energy usage. PARV-CE integrates quantization-aware execution with a reconfigurable SIMD pipeline, enabling high-throughput processing with minimal overhead through hardware-software co-design. The results demonstrate up to 2x improvement in PDP and 3x reduction in resource usage compared to SoTA designs, while retaining accuracy within 1.8% FP32 baseline. The architecture supports both on-device training and inference across a range of workloads, including DNNs, RNNs, RL, and Transformer models. The empirical analysis establish PARVCE incorporated POLARON as a scalable and energy-efficient solution for precision-adaptive AI acceleration at edge.