2024/08/20 by Laslo Hunhold, Hunhold, Laslo · 1 citation
Computer Science · #68M07 #B.2.1 #B.2.2 #Embedded Systems Design Techniques #FOS: Computer and information sciences #Hardware Architecture (cs.AR)
paper · pdf · doi:10.48550/arxiv.2408.10594
openalex publication_date 2024/08/20 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/31
The takum machine number format has been recently proposed as an enhancement over the posit number format, which is considered a promising alternative to the IEEE 754 floating-point standard. Takums retain the useful posit properties, but feature a novel exponent coding scheme that yields more precision for small and large magnitude numbers and a much higher and bounded dynamic range. This paper presents the design and implementation of a hardware codec for both takums (logarithmic number system, LNS) and linear takums (floating-point format). The codec design is emphasised, as it constitutes the primary distinguishing feature compared to logarithmic posits (LNS) and posits (floating-point format), which otherwise share similar internal representations. Furthermore, a novel internal representation for LNS is proposed. The presented takum codec, implemented in VHDL, demonstrates near-optimal scalability and performance on an FPGA. It achieves latency reductions of up to 38% and reduces LUT utilisation up to 50% compared to the best state-of-the-art posit codecs.