2025/08/28 by González, J. L., Cruz, J. C., Moreno, R. L. +1 · 2 citations
#FOS: Electrical engineering #Systems and Control (eess.SY) #electronic engineering #information engineering
paper · doi:10.48550/arxiv.2508.20611
This paper studies an architecture with digitally controllable gain and power consumption to mitigate the impact of process variations on CMOS low-noise amplifiers (LNAs). A \SI130nm, \SI1.2V LNA implementing the proposed architecture is designed based on an analysis of variability in traditional LNAs under different bias currents and on the corresponding effects on the performance of a complete receiver. Two different adjustment strategies are evaluated, both of which are compatible with previously reported built-in self-test (BIST) circuits. Results show that the proposed architecture enables yield enhancement while keeping low-power operation compared with traditional LNAs.