2020/01/15 by Lizhou Wu, Mottaqiallah Taouil, Wu, Lizhou +7
Engineering · #68-02 #A.1 #Emerging Technologies (cs.ET) #FOS: Computer and information sciences #Integrated Circuits and Semiconductor Failure Analysis #Non-Destructive Testing Techniques #Semiconductor materials and devices
paper · pdf · doi:10.48550/arxiv.2001.05463
openalex publication_date 2020/01/15 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
As one of the most promising emerging non-volatile memory (NVM) technologies, spin-transfer torque magnetic random access memory (STT-MRAM) has attracted significant research attention due to several features such as high density, zero standby leakage, and nearly unlimited endurance. However, a high-quality test solution is required prior to the commercialization of STT-MRAM. In this paper, we present all STT-MRAM failure mechanisms: manufacturing defects, extreme process variations, magnetic coupling, STT-switching stochasticity, and thermal fluctuation. The resultant fault models including permanent faults and transient faults are classified and discussed. Moreover, the limited test algorithms and design-for-testability (DfT) designs proposed in the literature are also covered. It is clear that test solutions for STT-MRAMs are far from well established yet, especially when considering a defective part per billion (DPPB) level requirement. We present the main challenges on the STT-MRAM testing topic at three levels: failure mechanisms, fault modeling, and test/DfT designs.