2018/12/23 by Xavier Timoneda, Timoneda, Xavier, Sergi Abadal +13 · 3 citations
Computer Science · Engineering · #FOS: Computer and information sciences #Interconnection Networks and Systems #Microwave Engineering and Waveguides #Networking and Internet Architecture (cs.NI) #Radio Frequency Integrated Circuit Design
paper · pdf · doi:10.48550/arxiv.1901.04291
openalex publication_date 2018/12/23 · openalex created_date 2022/08/01 · openalex updated_date 2026/07/28
Ubiquitous multicore processors nowadays rely on an integrated\npacket-switched network for cores to exchange and share data. The performance\nof these intra-chip networks is a key determinant of the processor speed and,\nat high core counts, becomes an important bottleneck due to scalability issues.\nTo address this, several works propose the use of mm-wave wireless\ninterconnects for intra-chip communication and demonstrate that, thanks to\ntheir low-latency broadcast and system-level flexibility, this new paradigm\ncould break the scalability barriers of current multicore architectures.\nHowever, these same works assume 10+ Gb/s speeds and efficiencies close to 1\npJ/bit without a proper understanding on the wireless intra-chip channel. This\npaper first demonstrates that such assumptions do not hold in the context of\ncommercial chips by evaluating losses and dispersion in them. Then, we leverage\nthe system's monolithic nature to engineer the channel, this is, to optimize\nits frequency response by carefully choosing the chip package dimensions.\nFinally, we exploit the static nature of the channel to adapt to it, pushing\nefficiency-speed limits with simple tweaks at the physical layer. Our methods\nreduce the path loss and delay spread of a simulated commercial chip by 47 dB\nand 7.3x, respectively, enabling intra-chip wireless communications over 10\nGb/s and only 3.1 dB away from the dispersion-free case.\n