VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation

2025/07/09 by Paul E. Calzada, Zahin Ibnat, Calzada, Paul E. +13 · 4 citations
Computer Science · Materials Science · #Artificial Intelligence (cs.AI) #Embedded Systems Design Techniques #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Machine Learning (cs.LG) #Machine Learning in Materials Science #Parallel Computing and Optimization Techniques

paper · pdf · doi:10.48550/arxiv.2507.13369

openalex publication_date 2025/07/09 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

Large Language Models (LLMs) are gaining popularity for hardware design automation, particularly through Register Transfer Level (RTL) code generation. In this work, we examine the current literature on RTL generation using LLMs and identify key requirements for training and fine-tuning datasets. We construct a robust Verilog dataset through an automated three-pronged process involving database (DB) creation and management with PostgreSQL, data collection from code hosting sites like OpenCores and GitHub, and data preprocessing to verify the codes' syntax, run logic synthesis, and extract relevant module metadata. We implement a scalable and efficient DB infrastructure to support analysis and detail our preprocessing pipeline to enforce high-quality data before DB insertion. The resulting dataset comprises 20,392 Verilog samples, 751 MB of Verilog code data, which is the largest high-quality Verilog dataset for LLM fine-tuning to our knowledge. We further evaluate the dataset, address associated challenges, and explore potential applications for future research and development in LLM-based hardware generation.

Citations

• ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification
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Cited by

• Mitigating hallucinations and omissions in LLMs for invertible problems: An application to hardware logic design automation
• Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead
• DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Base
• Retrieval-Augmented Code Generation: A Survey with Focus on Repository-Level Approaches

Related

• Benchmarking Large Language Models for Automated Verilog RTL Code Generation
• RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects
• SysVCoder: An LLM-Driven Framework for Systematic Generation of System-Level Design
• Evaluating Large Language Models for Automatic Register Transfer Logic Generation via High-Level Synthesis
• Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead