2022/12/11 by Bo Ding, Jinglei Huang, Ding, Bo +9
Computer Science · Engineering · #Embedded Systems Design Techniques #FOS: Electrical engineering #Interconnection Networks and Systems #Systems and Control (eess.SY) #VLSI and FPGA Design Techniques #electronic engineering #information engineering
paper · pdf · doi:10.48550/arxiv.2212.05397
openalex publication_date 2022/12/11 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Modern field programmable gate array(FPGA) can be partially dynamically reconfigurable with heterogeneous resources distributed on the chip. And FPGA-based partially dynamically reconfigurable system(FPGA-PDRS) can be used to accelerate computing and improve computing flexibility. However, the traditional design of FPGA-PDRS is based on manual design. Implementing the automation of FPGA-PDRS needs to solve the problems of task modules partitioning, scheduling, and floorplanning on heterogeneous resources. Existing works only partly solve problems for the automation process of FPGA-PDRS or model homogeneous resource for FPGA-PDRS. To better solve the problems in the automation process of FPGA-PDRS and narrow the gap between algorithm and application, in this paper, we propose a complete workflow including three parts, pre-processing to generate the list of task modules candidate shapes according to the resources requirements, exploration process to search the solution of task modules partitioning, scheduling, and floorplanning, and post-optimization to improve the success rate of floorplan. Experimental results show that, compared with state-of-the-art work, the proposed complete workflow can improve performance by 18.7%, reduce communication cost by 8.6%, on average, with improving the resources reuse rate of the heterogeneous resources on the chip. And based on the solution generated by the exploration process, the post-optimization can improve the success rate of the floorplan by 14%.