2024/04/12 by Ghassem Jaberipur, Jaberipur, Ghassem, Bardia Nadimi +3 · 1 citation
Computer Science · #Coding theory and cryptography #Cryptography and Residue Arithmetic #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Numerical Methods and Algorithms
paper · pdf · doi:10.48550/arxiv.2404.08228
openalex publication_date 2024/04/12 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Augmenting the balanced residue number system moduli-set \m1=2n,m2=2n-1,m3=2n+1\, with the co-prime modulo m4=22n+1, increases the dynamic range (DR) by around 70%. The Mersenne form of product m2 m3 m4=24n-1, in the moduli-set \m1,m2,m3,m4\, leads to a very efficient reverse convertor, based on the New Chinese remainder theorem. However, the double bit-width of the m4 residue channel is counter-productive and jeopardizes the speed balance in \m1,m2,m3\. Therefore, we decompose m4 to two complex-number n-bit moduli 2n±√(-1), which preserves the DR and the co-primality across the augmented moduli set. The required forward modulo-(22n+1) to moduli-(2n±√(-1)) conversion, and the reverse are immediate and cost-free. The proposed unified moduli-(2n±√(-1)) adder and multiplier, are tested and synthesized using Spartan 7S100 FPGA. The 6-bit look-up tables (LUT), therein, promote the LUT realizations of adders and multipliers, for n=5, where the DR equals 225-25. However, the undertaken experiments show that to cover all the 32-bit numbers, the power-of-two channel m1 can be as wide as 12 bits with no harm to the speed balance across the five moduli. The results also show that the moduli-(25±√(-1)) add and multiply operations are advantageous vs. moduli-(25±1) in speed, cost, and energy measures and collectively better than those of modulo-(210+1).