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CMOS on-chip thermometry at deep cryogenic temperatures

2023/08/01 by Grayson M. Noah, Thomas Swift, Noah, Grayson M. +9 · 4 citations
Engineering · Materials Science · #Advancements in Semiconductor Devices and Circuit Design #Applied Physics (physics.app-ph) #FOS: Physical sciences #Heat Transfer and Boiling Studies #Mesoscale and Nanoscale Physics (cond-mat.mes-hall) #Quantum Physics (quant-ph) #Thermal properties of materials

paper · pdf · doi:10.48550/arxiv.2308.00392

openalex publication_date 2023/08/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

Accurate on-chip temperature sensing is critical for the optimal performance of modern CMOS integrated circuits (ICs), to understand and monitor localized heating around the chip during operation. The development of quantum computers has stimulated much interest in ICs operating a deep cryogenic temperatures (typically 0.01 - 4 K), in which the reduced thermal conductivity of silicon and silicon oxide, and the limited cooling power budgets make local on-chip temperature sensing even more important. Here, we report four different methods for on-chip temperature measurements native to complementary metal-oxide-semiconductor (CMOS) industrial fabrication processes. These include secondary and primary thermometry methods and cover conventional thermometry structures used at room temperature as well as methods exploiting phenomena which emerge at cryogenic temperatures, such as superconductivity and Coulomb blockade. We benchmark the sensitivity of the methods as a function of temperature and use them to measure local excess temperature produced by on-chip heating elements. Our results demonstrate thermometry methods that may be readily integrated in CMOS chips with operation from the milliKelivin range to room temperature.

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